Burg Altena, Germany
The Rhode Island Computer Museum, Inc.
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Astronautics ZS-1
Astronautics ZS-1, S/N 005

During January 2002 Merle Pierce drove to Wisconsin to retreive this Astronautics ZS-1 system. Jon Auringer and Andre Boeder of Astronautics, Richard Shauer, Jerry ?, and ?, of the Illinois Railway Museum's Trackless Department, and Gunter Schadow assisted in loading the equipment in Wisconsin. This machine was designed by Dr. James E. Smith when he worked for the Astronautics Corporation of America in Madison, WS. The CPU is DAE (decoupled access/execute) architecture which increases the amount of parallelism and can hide a large amount of memory latency. The CPU provides 45 MIPS and 22.5 MFLOPS peak ,has 64 bit floating point, and 128KBytes of cache. The Interconnect Network has 1.42 GBytes/s bandwidth and the I/O Multiplexer provides an aggregate of 180 MBytes/s of bandwidth. The system supports a maximum of 256 MBytes of 16 way interleaved memory with a bandwidth of 350 MBytes/s. The decoupled architecture allows the CPU to fetch a maximum of two instructions per 45 ns clock period. The two instructions are split into individual steams and are then processed by its own pipeline. One pipeline containe the "A" instructions and does all of the memory accesses. The other pipeline contains the "X" instructions and does the floating point operations. Several instructions may be in some phase of execution concurently. The access and execution sections are connected with queues. The queues are buffered seperately which allows the access instruction stream to run ahead of the execute instruction stream. This results in a major reduction in memory access time. The system runs 4.3 BSD UNIX. The Fortran compiler creates code that optimizes the performance of the pipelines. The compiler also unrolls loops to reduce the number of branch instructions that are executed. This machine was the first production quality system and is the only ZS-1 that is not in possession of Astronautics

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